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Digital-techniques-microprocessors
Basic Digital Techniques & Applications - PART 1
We regularly use many electronic gadgets like computers and mobiles
in our day to day life, but have we ever thought of the basic logic behind
these systems? This article gives the detailed answer to the question just
asked. Yes, correct, it’s the digital techniques!
1. Introduction:
May it beany type of work; we make use of, rather need
IT resources.So, let us have a look at the basic concept behind all these
digital techniques. The name digital indicates that the working principle
consists of digit or number of digits. It is a method of representing a number
by discrete units. The digit means a single symbol of a number system, whereas
a ‘Bit’ means binary digit.
1.1 Number
Systems:
We use number systems to count various items. Just
after hearing the word ‘number’, we must have thought of the basic numbering
system, The Decimal System i.e. numbers 0,1,2,3,…… up to 9. Modern gadgets like
computers,for communication and operation, need only 2 of the decimal numbers.
Those are 0 and 1. This number system is known as the Binary Number System or
base ‘2’ system, where in each number (0 and 1) is known as a ‘bit’. For more
information, 4 bits = 1 nibble and 8 bits = 1 byte.
Every decimal number can be converted to binary and vice-versa.
0 – 0000
1 – 0001
2 – 0010
3 – 0011
4 –0100
5 – 0101
6 – 0110
7 – 0111
8 – 1000
9 – 1001
The binary number has a representation as shown in below diagram:
Now we will represent some of above decimal numbers as binary:
Decimal 1:
Representation:
Number = … + 0 x 23+ 0 x 22+ 0 x 21 +
1 x 20 = ….+ 0 + 0 + 0 + 1 x 1 = 1 (Decimal 1)
Here, 23,
22, 21, 20 are the multipliers, where the
superscript mentions position and base is 2 since its binary representation. Each
multiplier is multiplied with the binary digits at that position.
Multiplication of each place is added finally to get the decimal number.
Decimal 2:
Number = … + 0 x 23+ 0 x 22 + 1 x 21 +
0 x 20 = ….+ 0 + 0 + 2 + 0 = 2 (Decimal 2)
Decimal 3:
Number = … + 0 x 23+ 0 x 22 + 1 x 21 +
1 x 20 = ….+ 0 + 0 + 2 + 1 = 3 (Decimal 3)
And so on......
(to be continued.... PART 2)
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Digital-techniques-microprocessors
Digital Techniques and Microprocessor - PART 11
DelayFlip-flops:
If we use only middle two rows of truth table of S/R
or J/K flip-flop, we obtain D flip-flop. It has only 1 data input. Output is
obtained at Qn+1 that is, at the end of clock pulse which is equal
to input Dnwhich is applied at beginning or before clock pulse. This
is equivalent to saying that input data appears at output at the end of clock
pulse. Thus, the transfer of data from input to output is delayed by one clock
pulse. Hence, the flip-flop is named as Delay flip-flop (D). Delay flip-flop is
either used as a delay device or as a latch to store 1 bit binary information.
Dn
|
Qn+1
|
Input
|
Output
|
0
|
0
|
1
|
1
|
7) Toggle Flip-flops:
In J-K flip-flop if J = K the resulting flip-flop is
referred to as Toggle flip-flop. It has only 1 input. If T = 1, it acts as a
Toggle switch. For every clock pulse output changes. S-R flip-flop cannot be
converted directly into Toggle flip-flop since in S, R S = R = 1 is not
allowed.
Tn
|
Qn+1
|
Input
|
Output
|
0
|
Qn
|
1
|
 |
Applications of
Flip-flops:
1. Bounce elimination switch
2. Latch
3. Register
4. Counter
5. Memory
This was all about the basic gates, their functioning,
truth tables and their applications. There are many other applications like
Registers, Counters, and Microprocessors which have these logic gates as a
basic circuitry in them. There are many integrated circuits and chips which are
the heart of many appliances we use daily have logic gates and digital logic. Thus,
it has become very important for us to know at least the basics of Boolean
logic and logic gates.
Digital-techniques-microprocessors
Digital Techniques and Applications - PART 9
Sequential Logic Circuits
In digital circuit theory, sequential logic is a type
of logic circuit whose output depends not only on the present value of its
input signals but on the sequence of past inputs, the input history. This is in
contrast to combinational logic, whose output is a function of only the present
input. That is, sequential logic has memory while combinational logic does not.
Or, in other words, sequential logic is combinational logic with memory.
A familiar example of a device with sequential logic
is a television set with "channel up" and "channel down"
buttons. Pressing the "up" button gives the television an input
telling it to switch to the next channel above the one it is currently
receiving. If the television is on channel 5, pressing "up" switches
it to receive channel 6. In order for the channel selection to operate correctly,
the television must be aware of which channel it is currently receiving, which
was determined by past channel selections. The television stores the current
channel as part of its state. When a
"channel up" or "channel down" input is given to it, the
sequential logic of the channel selection circuitry calculates the new channel
from the input and the current channel.Hence, the television stores the past input
state. Hence, the television can be
termed as a sequential logic circuit.
In synchronous sequential circuits, the state of the
device changes only at discrete times in response to a clock signal. The device
used for timing purposes is known as system clock. In asynchronous circuits the
state of the device can change at any time in response to changing inputs.
Let us look at the examples of Sequential Logic
Circuits:
As we have already seen, logic circuit is a connection
of logic gates. A sequential logic circuit is circuit whose output depends upon
input and last output.
1) 1 Bit Memory
cell Flip-flops:
Flip-flop is a 1 bit memory cells made up of logic
gates. Generally flip-flops are used in groups. It can store either logic 1
(state 1) or logic 0 (state 0). It is a basic digital memory consisting of 2
inverting NAND gates. The output of first NAND gate (G1) is connected to input
of second NAND gate (G2) and vice versa.
Let’s take a scenario where we would assume output of
first NAND gate G1 = Q = 1. Because of interconnection of these two NAND gates,
input of second NAND gate G2 = I2 = 1. Because of this, output of second NAND
gate G2 = Q compliment = 0 which will be input of first NAND gate = 0
which makes Q = 1. This confirms our assumption.
There are few points worth noting:
1) The outputs Q and Q bar (Q compliment) are always complementary to each other.
2) The circuit has 2 stable states. In one of the
stable state Q = 1 which is referred to as ‘set’ state whereas in other state
Q=0. It is referred as ‘reset’ state.
3) If the circuit is in ‘set’ state, it continues to
remain in that state & similarly if it is in ‘reset ‘state, then it
continues to remain in ‘reset’ state. This property of a circuit is referred to
as memory. That is, it can store one bit of digital information.
Since the information is locked or latched in this
circuit therefore the circuit is also known as a ‘latch’.
2) Set-Reset Flip-flops:
In one bit memory cell, there is no way of entering
the desired information to be stored in it. In fact if power is given to the
circuit, the circuit state will be stable, but unpredictable. Hence, in order
to overcome this difficulty, if we replace the gates G1 and G2 with the 2 input
NAND gate, then the circuit can be used to enter desired digital information.
S
|
R
|
Output
|
0
|
0
|
Previous Output
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
Not Allowed
|
Let us test each row in the truth table.
When S=0 R=1:
Let us assume initially Q = 0 and Q bar = 1 and Output Gate 3, G3 = 1 and that of G4 =
0. With all these conditions, according to the truth table of NAND gate,
assumption is proved.
Now we assume Q = 1 and Q bar = 0. In this case too if we consider G3 = 1
and G4 = 0, the output of gate 2 G2 = Q bar = 1. Which in turn causes output of gate G1 =
Q = 0. This contradicts our assumption. So, when reset pin is logic 1 (high),
irrespective of past output, the output becomes reset (logic 0).
When S=1 R=0:
Initially assume Q = 0 and Q bar = 1. When S = 1, output of G3 = 0 and that of
G4 = 1. Now according to the truth table of NAND gate, Q = 1 and Q bar = 0. That contradicts our assumption of Q = 0.
Hence, that means, when Set pin (S) is 1, irrespective of past output,
flip-flop output is set i.e. 1.
When S=0, R=0:
In this case, the output of NAND gate G3 and G4 = 1.
Assume Q = 0 and Q bar = 1. This satisfies our assumption. Now we
will assume Q = 1 and Q bar = 0. This too satisfies our assumption.
Thus, in S-R flip-flop when S and R both are 0, the
output is same as past output.
When S=1, R=1:
In this case, the output of NAND gate G3 and G4 = 0. Assume
Q = 0 and Q bar = 1. But at the end, when we calculate logic
of NAND gates, outputs become Q = 1 and Q bar = 1. Thus this case is not allowed. The same
thing happens when we assume Q = 1 and Q bar = 0 initially.
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Digital-techniques-microprocessors
Digital Techniques and Applications - PART 10
Clocked Set-Reset Flip-flops:
It is often required to set or reset the memory cell
in synchronization with a train of pulses known as clock and circuit is
referred to as Clocked S-R flip-flop. When CLK (Clock) input pulse is present, it’ssame
as S-R flip-flop.When clock pulse is absent, outputs are 1 irrespective of
values of S and R.
In flip-flop when power is switched ON, the state of a
circuit is uncertain. It may come to Set (Q = 1) or Reset (Q = 0). To set or
reset flip-flop initially, initial state is assigned to flip-flop using direct
or asynchronous inputs referred to as Preset (Pr) or Clear (Cr). These inputs
may be applied at any time between clock pulses and are not in synchronization.
Truth
Table:
Sn
|
Rn
|
Qn+1
|
0
|
0
|
Qn
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
Not Allowed
|
In the above truth table, ‘n’ indicates the clock
cycle. Sn and Rn are inputs to circuit at nth clock
cycle. Qn+1 is the output of a circuit in next clock pulse. As in
case of normal S-R flop-flop, when S=R=0, it gives past output (Qn).
4) J-K Flip-flops:
The uncertainty in the state of S-R flip-flop when Sn
= Rn = 1 can be eliminated by converting S-R flip-flop into JK
flip-flop.
Truth
Table:
Jn
|
Kn
|
Qn+1
|
0
|
0
|
Qn
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
Qn bar
|
As we can see in the diagram, the output Q bar is directly connected to NAND gate number 3
and Q is connected to NAND gate number 4. As we can see in the truth table,
when Jn = Kn = 1, the output is Qn bar. That is
the complement of the output of previous clock cycle. In this way, the uncertainty
is avoided in case of J-K flip-flop by means of feedback connection.
Every logic gate has some amount of propagation delay.
Propagation delay is the amount of time required for the logic gate to produce
stable output after stable and proper input is applied to it.
Because of this, when J = K = 1 & Q = 0, after
propagation delay, theoutput will change to Q = 1. Now it becomes J = K = 1 and
Q = 1. After another time interval of propagation delay, output will change
back to Q = 0. This situation in which value of Q becomes uncertain is referred
to as Race AroundCondition. This is the
drawback of J-K flip-flop. In order to avoid this difficulty, Master-Slave J-K
flip-flop MSJK flip-flop is used.
5) Master-Slave J-K Flip-flops:
MSJK flip-flop is cascade of 2 S-R flip-flop with
feedback from outputs of second to the input of first. Positive clock pulse is
applied to input of first and negative to second.
When clock is 1, the first flip-flop is enabled and
output Qm and Qm bar responds to input J & K. At this time,
second flip-flop is disabled since its clock is low.
When clock is 0, master flip-flop is disabled whereas
slave flip-flop is enabled and it gives final output Q and
.Therefore,
the output Q and follows Qm
and 
. Since
output Q and are changing at negative clock pulse, the
clock shown in the MSJK flip-flop is negative (a bubble and a triangle). In this circuit the inputs to master flip-flop do not
change during clock pulse. They are entertained only in positive clock. Hence
race around condition is avoided.
.Therefore,
the output Q and follows Qm
and . Since
output Q and are changing at negative clock pulse, the
clock shown in the MSJK flip-flop is negative (a bubble and a triangle). In this circuit the inputs to master flip-flop do not
change during clock pulse. They are entertained only in positive clock. Hence
race around condition is avoided.
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