Digital-techniques-microprocessors
Digital Techniques and Applications - PART 10
Clocked Set-Reset Flip-flops:
It is often required to set or reset the memory cell
in synchronization with a train of pulses known as clock and circuit is
referred to as Clocked S-R flip-flop. When CLK (Clock) input pulse is present, it’ssame
as S-R flip-flop.When clock pulse is absent, outputs are 1 irrespective of
values of S and R.
In flip-flop when power is switched ON, the state of a
circuit is uncertain. It may come to Set (Q = 1) or Reset (Q = 0). To set or
reset flip-flop initially, initial state is assigned to flip-flop using direct
or asynchronous inputs referred to as Preset (Pr) or Clear (Cr). These inputs
may be applied at any time between clock pulses and are not in synchronization.
Truth
Table:
Sn
|
Rn
|
Qn+1
|
0
|
0
|
Qn
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
Not Allowed
|
In the above truth table, ‘n’ indicates the clock
cycle. Sn and Rn are inputs to circuit at nth clock
cycle. Qn+1 is the output of a circuit in next clock pulse. As in
case of normal S-R flop-flop, when S=R=0, it gives past output (Qn).
4) J-K Flip-flops:
The uncertainty in the state of S-R flip-flop when Sn
= Rn = 1 can be eliminated by converting S-R flip-flop into JK
flip-flop.
Truth
Table:
Jn
|
Kn
|
Qn+1
|
0
|
0
|
Qn
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
Qn bar
|
As we can see in the diagram, the output Q bar is directly connected to NAND gate number 3
and Q is connected to NAND gate number 4. As we can see in the truth table,
when Jn = Kn = 1, the output is Qn bar. That is
the complement of the output of previous clock cycle. In this way, the uncertainty
is avoided in case of J-K flip-flop by means of feedback connection.
Every logic gate has some amount of propagation delay.
Propagation delay is the amount of time required for the logic gate to produce
stable output after stable and proper input is applied to it.
Because of this, when J = K = 1 & Q = 0, after
propagation delay, theoutput will change to Q = 1. Now it becomes J = K = 1 and
Q = 1. After another time interval of propagation delay, output will change
back to Q = 0. This situation in which value of Q becomes uncertain is referred
to as Race AroundCondition. This is the
drawback of J-K flip-flop. In order to avoid this difficulty, Master-Slave J-K
flip-flop MSJK flip-flop is used.
5) Master-Slave J-K Flip-flops:
MSJK flip-flop is cascade of 2 S-R flip-flop with
feedback from outputs of second to the input of first. Positive clock pulse is
applied to input of first and negative to second.
When clock is 1, the first flip-flop is enabled and
output Qm and Qm bar responds to input J & K. At this time,
second flip-flop is disabled since its clock is low.
When clock is 0, master flip-flop is disabled whereas
slave flip-flop is enabled and it gives final output Q and
.Therefore,
the output Q and follows Qm
and 
. Since
output Q and are changing at negative clock pulse, the
clock shown in the MSJK flip-flop is negative (a bubble and a triangle). In this circuit the inputs to master flip-flop do not
change during clock pulse. They are entertained only in positive clock. Hence
race around condition is avoided.
.Therefore,
the output Q and follows Qm
and . Since
output Q and are changing at negative clock pulse, the
clock shown in the MSJK flip-flop is negative (a bubble and a triangle). In this circuit the inputs to master flip-flop do not
change during clock pulse. They are entertained only in positive clock. Hence
race around condition is avoided. 
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