Digital Techniques and Applications - PART 9

05:45:00 Nandan Bhalwankar 0 Comments

Sequential Logic Circuits

In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history. This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has memory while combinational logic does not. Or, in other words, sequential logic is combinational logic with memory.

A familiar example of a device with sequential logic is a television set with "channel up" and "channel down" buttons. Pressing the "up" button gives the television an input telling it to switch to the next channel above the one it is currently receiving. If the television is on channel 5, pressing "up" switches it to receive channel 6. In order for the channel selection to operate correctly, the television must be aware of which channel it is currently receiving, which was determined by past channel selections. The television stores the current channel as part of its state. When a "channel up" or "channel down" input is given to it, the sequential logic of the channel selection circuitry calculates the new channel from the input and the current channel.Hence, the television stores the past input state. Hence, the television can be termed as a sequential logic circuit.

In synchronous sequential circuits, the state of the device changes only at discrete times in response to a clock signal. The device used for timing purposes is known as system clock. In asynchronous circuits the state of the device can change at any time in response to changing inputs.

Let us look at the examples of Sequential Logic Circuits:

As we have already seen, logic circuit is a connection of logic gates. A sequential logic circuit is circuit whose output depends upon input and last output.

               

1) 1 Bit Memory cell Flip-flops:

Flip-flop is a 1 bit memory cells made up of logic gates. Generally flip-flops are used in groups. It can store either logic 1 (state 1) or logic 0 (state 0). It is a basic digital memory consisting of 2 inverting NAND gates. The output of first NAND gate (G1) is connected to input of second NAND gate (G2) and vice versa.

Let’s take a scenario where we would assume output of first NAND gate G1 = Q = 1. Because of interconnection of these two NAND gates, input of second NAND gate G2 = I2 = 1. Because of this, output of second NAND gate G2 = Q compliment = 0 which will be input of first NAND gate = 0 which makes Q = 1. This confirms our assumption.

There are few points worth noting:

1) The outputs Q and Q bar (Q compliment) are always complementary to each other.

2) The circuit has 2 stable states. In one of the stable state Q = 1 which is referred to as ‘set’ state whereas in other state Q=0. It is referred as ‘reset’ state.

3) If the circuit is in ‘set’ state, it continues to remain in that state & similarly if it is in ‘reset ‘state, then it continues to remain in ‘reset’ state. This property of a circuit is referred to as memory. That is, it can store one bit of digital information.

Since the information is locked or latched in this circuit therefore the circuit is also known as a ‘latch’.

2) Set-Reset Flip-flops:

In one bit memory cell, there is no way of entering the desired information to be stored in it. In fact if power is given to the circuit, the circuit state will be stable, but unpredictable. Hence, in order to overcome this difficulty, if we replace the gates G1 and G2 with the 2 input NAND gate, then the circuit can be used to enter desired digital information.

S	R	Output
0	0	Previous Output
0	1	0
1	0	1
1	1	Not Allowed

Let us test each row in the truth table.

When S=0 R=1:

Let us assume initially Q = 0 and Q bar = 1 and Output Gate 3, G3 = 1 and that of G4 = 0. With all these conditions, according to the truth table of NAND gate, assumption is proved.

Now we assume Q = 1 and Q bar = 0. In this case too if we consider G3 = 1 and G4 = 0, the output of gate 2 G2 = Q bar = 1. Which in turn causes output of gate G1 = Q = 0. This contradicts our assumption. So, when reset pin is logic 1 (high), irrespective of past output, the output becomes reset (logic 0).

When S=1 R=0:

Initially assume Q = 0 and Q bar = 1. When S = 1, output of G3 = 0 and that of G4 = 1. Now according to the truth table of NAND gate, Q = 1 and Q bar = 0. That contradicts our assumption of Q = 0. Hence, that means, when Set pin (S) is 1, irrespective of past output, flip-flop output is set i.e. 1.

When S=0, R=0:

In this case, the output of NAND gate G3 and G4 = 1. Assume Q = 0 and Q bar = 1. This satisfies our assumption. Now we will assume Q = 1 and Q bar = 0. This too satisfies our assumption.

Thus, in S-R flip-flop when S and R both are 0, the output is same as past output. 

When S=1, R=1:

In this case, the output of NAND gate G3 and G4 = 0. Assume Q = 0 and Q bar = 1. But at the end, when we calculate logic of NAND gates, outputs become Q = 1 and Q bar = 1. Thus this case is not allowed. The same thing happens when we assume Q = 1 and Q bar = 0 initially.